A 10 - bit , 100 MS / s , Pipeline Analog - to - Digital Converter Andres Tamez , Lukas C . Skoog , and Spencer Pace
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چکیده
—A 10-bit, 100 Ms/s switched capacitor pipeline A/D converter has been implemented in 0.25um CMOS in the 1.5-bit/stage architecture. Simulations results indicate 6.7 effective bits and max INL and DNL of 0.708 and 0.298 LSB, respectively. The design features a fully differential signal path and implements sub-ADC sections using a recently developed switched capacitor technique. Additionally, digital error correction uses the redundancy in each stage to relax comparator offset requirements. The converter in this paper would possess power and area advantages over similar architectures by reducing the required op-amp performance down the pipeline, and by making the 1x SHA at the front-end optional while maintaining overall ADC functionality.
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